Aviza Technology and SEZ Group Enter into Joint Development Agreement

11.07.2005, Collaboration to Focus on Backside and Bevel-Edge Removal Solutions for ALD Films.

SCOTTS VALLEY, Calif., and VILLACH, Austria, July 11, 2005—Aviza Technology, Inc., a global supplier of production-proven thermal process and atomic layer deposition (ALD) systems, and the SEZ Group (SWX: SEZN), the market leader and premier innovator in single-wafer wet processing solutions for the semiconductor industry, today announced they are joining forces to solve key challenges surrounding ALD film removal for next- generation IC manufacturing. Under a joint development agreement, both companies intend to leverage their expertise to develop solutions for deposition and removal of advanced films used in ALD applications, concentrating on the wafer backside and bevel edge.

“With the ever-increasing complexity of semiconductor devices, backside and bevel-edge film removal is playing an increasingly important role in the IC manufacturing process,” said Dr. Leo Archer, director of emerging technologies worldwide, SEZ. “Our collaboration with Aviza will be mutually rewarding, as we are both well positioned to address the intricacies of film deposition and removal at the sub-90-nm node. By developing, characterizing and refining processes for ALD film removal, we can provide our customers with the solutions they need to address advanced manufacturing challenges.”

Anneal conditions often dictate the degree of complexity associated with backside and bevel-edge film-removal processes. As levels of crystallization increase, annealed films require custom recipes and chemistries to ensure proper removal, while maintaining the integrity of film properties and decreasing cross contamination—resulting in increased yields. Due to their intricate composition, advanced films targeted for 45-nm high-ê gate dielectrics—such as hafnium oxide (HfO), hafnium silicate (HfSiO), and hafnium silicate oxynitride (HfSiO/N), as well as metals like ruthenium (Ru)—pose even greater challenges at these film-removal stages. The challenge is to selectively remove contamination caused by these materials from the backside and bevel edge of the wafer with a controlled wrap to the front side in order to prevent cross-contamination and particle generation. These can cause issues with device performance, film delamination, lithography problems, and ultimately, device yield. Selectivity is important because it is not always advantageous or possible to remove too much of the underlying substrate material, be it silicon, oxide, or nitride. Excessive etching can remove a necessary diffusion barrier and can affect wafer flatness and uniformity.

SEZ’s Spin Processor technology offers advantages for this sort of process, as it allows a patterned wafer to be processed face down on the patented Bernoulli chuck. Moreover, the combined chuck, chemical dispense system, and chamber allow highly controlled wraparound to the front side of the wafer to predefined distances.

“The development of materials and processes for ALD applications is key to accelerating the ALD roadmap and driving the adoption of ALD,” said Jon Owyang, director of ALD product management at Aviza Technology. “Aviza is continually evaluating and developing advanced films to complement next-generation manufacturing processes. By entering into a collaboration with SEZ, we intend to leverage our core areas of expertise to develop advanced manufacturing and process solutions for our customers that meet requirements for backside trace materials and backside particle levels.”

Aviza and the SEZ Group will be exhibiting at SEMICON West 2005, July 12-14, at the Moscone Convention Center in San Francisco. For more information about each company and its products, please visit Aviza in the South Hall at Booth #1616 or SEZ Group in the North Hall at Booth #5568.

About SEZ Group The SEZ Group is the leading provider of single-wafer, wet-processing solutions for the global semiconductor industry, with an installed base of over 900 tools. The company maintains operations in Asia-Pacific, Europe, Japan, and North America. SEZ Holding AG is traded on the SWX Swiss Exchange under the symbol SEZN. Additional information about the company is available on the Internet at www.sez.com.

About Aviza Technology, Inc. Aviza Technology is a supplier of thermal processing, low-pressure chemical vapor deposition and atomic layer deposition solutions to the global semiconductor industry. The company maintains a worldwide installed base of more than 2,500 tools. Aviza’s headquarters, manufacturing and R&D facilities are located in Scotts Valley, Calif. Additional sales and customer support facilities are located in Germany, France, Scotland, Taiwan, China, Japan, Singapore and Malaysia. Aviza has 500+ full-time employees and contractors worldwide. Additional information can be found at www.avizatechnology.com.

Über Lam Research Holding GmbH:

Lam Research Corporation has been a major supplier of wafer fabrication equipment and services to the worldwide semiconductor industry for nearly 30 years. As the industry transitions from business computer-based applications to feature-rich consumer products, chipmakers are challenged to mass produce highly sophisticated devices. To keep pace and meet demanding production requirements, semiconductor manufacturers will need to invest in highly versatile and reliable wafer fabrication equipment.

As the market leader in plasma etch and a leading supplier of single-wafer clean products, Lam Research strives to consistently deliver the technical capability and cost-effective performance our customers require. With corporate headquarters located in Fremont, California, the Company maintains a network of facilities throughout North America, Europe, and Asia to meet the complex and changing needs of its global customer base.

Plasma etch and wafer cleaning processes are critical steps semiconductor device manufacturing and used numerous times throughout chip fabrication. Etch processes are used to create the finely delineated features in conductive and dielectric layers. Wafer cleaning removes residues and particles after etch or photoresist strip or to prepare a wafer surface for subsequent processing steps. With each new technology node, the number and complexity of etch and clean steps increase significantly, providing ongoing need for innovation.

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